RV32 RISC-V Processor
Custom RV32 processor implemented in Verilog RTL with an 8-stage pipeline, branch prediction and cache optimization.
RV32IM
VERILOG
FPGA
250MHz
PROCESSOR UTILIZATION
SYSTEM MEMORY
ROOT FILESYSTEM
Custom RV32 processor implemented in Verilog RTL with an 8-stage pipeline, branch prediction and cache optimization.
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ceylan@engineering-node
ceylan@lab:~$ uname -a
Linux Engineering-Node x86_64 GNU/Linux
ceylan@lab:~$ ./build_future.sh
[ OK ] Loading RISC-V architecture
[ OK ] Initializing FPGA toolchain
[ OK ] Starting engineering node
BUILD SUCCESS
ceylan@lab:~$ █